View SFH6319T_295759.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EW
SFH6318T SFH6319T
LOW CURRENT, HIGH GAIN OPTOCOUPLER
Package Dimensions in Inches (mm)
.120.002 (3.05.05) NC 1
8 VCC 7 VB 6 V0 5 GND
N
FEATURES
* Industry Standard SOIC-8 Surface Mountable Package * High Current Transfer Ratio, 800% * Low Input Current, 0.5mA * High Output Current, 60mA * Isolation Test Voltage, 2500 VACRMS * TTL Compatible Output, VOL=0.1 V * Adjustable Bandwidth-Access to Base * Underwriters Lab File #E52744 * Available in Tape and Reel (suffix T) APPLICATIONS * Logic Ground Isolation-TTL/TTL, TTL/CMOS, CMOS/CMOS, CMOS/TTL * EIA RS 232C Line Receiver * Low Input Current Line Receiver-Long Lines, Party Lines * Telephone Ring Detector * 117 VAC Line Voltage Status Indication-Low Input Power Dissipation * Low Power Systems-Ground Isolation
.240 (6.10)
C .154.002 L (.391.05)
.016 (.41) .192.005 (4.88.13)
Anode 2 Cathode 3 NC 4 40
Pin 1
.015.002 (.38.05)
7 .058.005 (1.49.13) .125.005 (3.18.13) Lead Coplanarity .0015 (.04 max.
.004 (.10) .008 (.20)
.008 (.20) 5 max. R.010 (.25) max.
.021 (.53)
.050 (1.27) typ.
.020.004 (.15.10) 2 plcs.
TOLERANCE: .005 (unless otherwise noted)
DESCRIPTION
Very high current ratio together with 2500 VAC isolation are achieved by coupling an LED with an integrated high gain photodetector in a SOIC-8 package. Separate pins for the photodiode and output stage enable TTL compatible saturation voltages with high speed operation. Photodarlington operation is achieved by tying the VCC and VO terminals together. Access to the base terminal allows adjustment to the gain bandwidth. The SFH6318T is ideal for TTL applications since the 300% minimum current transfer ratio with an LED current of 1.6 mA enables operation with one unit load-in and one unit load-out with a 2.2 K pull-up resistor. The SFH6319T is best suited for low power logic applications involving CMOS and low power TTL. A 400% current transfer ratio with only 0.5 mA of LED current is guaranteed from 0C to 70C.
Caution: Due to the small geometries of this device, it should be handled with Electrostatic Discharge (ESD) precautions. Proper grounding would prevent damage further and/or degradation which may be induced by ESD.
Maximum Ratings (25) Emitter Reverse Input Voltage.............................................................. 3 V Supply and Output Voltage, VCC (pin 8-5), VO (pin 6-5) SFH6318T ..................................................................-0.5 to 7 V SFH6319T ................................................................-0.5 to 18 V Input Power Dissipation ..................................................... 35 mW Derate Linearly above 50C Free Air Temperature................................................ 0.7 mW/C Average Input Current......................................................... 20 mA Peak Input Current .............................................................. 40 mA (50% Duty Cycle-1 ms pulse width) Peak Transient Input Current (tp1 sec, 300 pps) ......................................................... 1.0 A Detector (Si Photodiode + Photodarlington) Output Current IO (pin 6)..................................................... 60 mA Emitter-Base Reverse Voltage (pin 5-7)................................ 0.5 V Output Power Dissipation................................................. 150 mW Derate Linearly from 25C ........................................... 2 mW/C Package Storage Temperature ......................................... -55C to +125C Operating Temperature........................................ -40C to +85C Lead Soldering Temperature (t=10 sec.).............................260C Junction Temperature ..........................................................100C Ambient Temperature Range............................. -55C to +100C IsolationTest Voltage between Emitter and Detector............................................ 2500 VACRMS (refer to climate DIN 40046, part 2, Nov. 74) Pollution Degree (DIN VDE 0110) ................................................2 Creepage Distance .............................................................4 mm Clearance............................................................................4 mm Comparative Tracking Index per DIN IEC 112/VDE 0303, part 1 .......................................175 Isolation Resistance VIO=500 V, TA=25C RISOL .............................................1012 VIO=500 V, TA=100C RISOL ...........................................1011
Semiconductor Goup
4-48
10.95
This document was created with FrameMaker 4.0.3
Electro-Optical Characteristics (TA=0C to 70C, TA=25C-Typical, unless otherwise specified)
Parameter Current Transfer Ratio Symbol CTR Device SFH6318T SFH6319T Min 300 400 500 Typ 1600 1600 2000 0.1 0.1 0.15 0.25 0.1 0.05 0.2 0.01 1.4 -1.8 Max 2600 2600 3500 0.4 0.4 0.4 0.4 250 100 1.5 10 1.7 Units % % Test Conditions IF=1.6 mA, VO=0.4 V, VCC=4.5 V IF=0.5 mA, VO=0.4 V, VCC=4.5 V IF=1.6 mA, VO=0.4 V, VCC=4.5 V IF=1.6 mA, IO=4.8 mA, VCC=4.5 V IF=1.6 mA, IO=8 mA, VCC=4.5 V IF=5 mA, IO=15 mA, VCC=4.5 V IF=12 mA, IO=24 mA, VCC=4.5 V IF=0 mA, VO=VCC=7 V IF=0 mA, VO=VCC=18 V IF=1.6 mA, VO=OPEN, VCC=18 V IF=0 mA, VO=OPEN, VCC=18 V IF=1.6 mA, TA=25C IF=1.6 mA f=1 MHz, VF=0 VIO=500 VDC, TA=25C VIO=500 VDC, TA=100C f=1 MHz 3 Note 1,2 1,2
Logic Low Output Voltage
VOL
SFH6318T SFH6319T
V V
2 2
Logic High Output Current Logic Low Supply Current Logic High Supply Current Input Forward Voltage Temperature Coefficient, Forward Voltage Input Capacitance Resistance (Input-Output)
IOH
SFH6318T SFH6319T
A A mA A V mV/ C pF pF
2 2 2 2
ICCL ICCH VF VF/TA CIN RI-O CI-O
25 1012 1011 0.6
Capacitance (Input-Output)
3
Switching Specifications (TA=25C)
Parameter Propagation Delay Time To Logic Low at Output Symbol tPHL Device SFH6318T SFH6319T Min Typ 2 6 0.6 2 4 1.5 1K Max 10 25 1 35 60 7 Units s s s s V/s Test Conditions IF=1.6 mA, RL=2.2 K IF=0.5 mA, RL=4.7 K IF=12 mA, RL=270 IF=1.6 mA, RL=2.2 K IF=0.5 mA, RL=4.7 K IF=12 mA, RL=270 IF=0 mA, RL=2.2 K VCM=10 Vp-p IF=1.6 mA, RL=2.2 K VCM=10 Vp-p 2,4 2,4 Note
Propagation Delay Time To Logic High at Output
tPLH
SFH6318T SFH6319T
Common Mode Transient Immunity at Logic High Level Output Common Mode Transient Immunity at Logic Low Level Output
| CMH |
5,6
| CML|
1K
V/s
5,6
Notes 1. DC current transfer ratio is defined as the ratio of outpput collector current, IO, to the forward LED input current, IF times 100%. 2. Pin 7 open. 3. Device considered a two-terminal device: pins 1, 2, 3 and 4 shorted together and pins 5, 6, 7 and 8 shorted together. 4. Using a resistor between pin 5 and 7 will decrease gain and delay time. 5. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the commomode pulse, VCM, to assure that the output will remain in a logic high state (i.e. VO>2.0 V) common mode transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode puse signal, VCM, to assure that the output will remain in a logic low state (i.e. VO<0.8 V). 6. In applications where dv/dt may exceed 50,000 V/s (such as state discharge) a series resistor, RCC should be included to protect IC from destructively high surge currents. The recommended value is RCC k. Refer to Figure 2. IV
0.15 IF(mA)
SFH6318T/6319T Semiconductor Group 4-49
Figure 1. Switching test circuit
IF 0 VO (Saturated Response) 1.5 V tPHL VO 90% (Non-Saturated Response) 10% tf tPLH 90% 10% tr 5V Rm 1.5 V VOL 5V Pulse Generator ZO=50 tr=5 ns IF 10% Duty Cycle 1/f<100 s
1 2 3
IF=Monitor
8 7
RL
+5 V
6 5
0.1 F
VO CL=15pF
4
Figure 2. Test circuit for transient immunity and typical waveforms RCC (see Note 6) VCM 0 V 10% tr tf + tf=16 ns VO Switch at A: IF=0 mA 90% 90% 10% tf A 5V B
1
IF
8 7 6 5
VCM
220 0.1 F RL
+5 V
2 3 4
VFF + -
VO
VO Switch at B: IF=1.6 mA
VOL
Pulse Generator
SFH6318T/6319T Semiconductor Group 4-50

▲Up To Search▲

Price & Availability of SFH6319T

	To Download SFH6319T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .